tm 74vhc373 octal d-type latch with 3-state outputs april 2007 ?993 fairchild semiconductor corporation www.fairchildsemi.com 74vhc373 rev. 1.3 74vhc373 octal d-type latch with 3-state outputs features high speed: t pd = 5.0ns (typ) @ v cc = 5v high noise immunity: v nih = v nil = 28% v cc (min.) power down protection is provided on all inputs low noise: v olp = 0.6v (typ.) low power dissipation: i cc = 4? (max) @ t a = 25? pin and function compatible with 74hc373 general description the vhc373 is an advanced high speed cmos octal d-type latch with 3-state output fabricated with silicon gate cmos technology. it achieves the high speed oper- ation similar to equivalent bipolar schottky ttl while maintaining the cmos low power dissipation. this 8-bit d-type latch is controlled by a latch enable input (le) and an output enable input (oe ). the latches appear transparent to data when latch enable (le) is high. when le is low, the data that meets the setup time is latched. when the oe input is high, the eight outputs are in a high impedance state. an input protection circuit ensures that 0v to 7v can be applied to the input pins without regard to the supply voltage. this device can be used to interface 5v to 3v systems and two supply systems such as battery back up. this circuit prevents device destruction due to mis- matched supply and input voltages. ordering information surface mount packages are also available on tape and reel. specify by appending the suffix letter ??to the ordering number. pb-free package per jedec j-std-020b. connection diagram pin descriptions order number package number package description 74vhc373m m20b 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide 74vhc373sj m20d 20-lead small outline package (sop), eiaj type ii, 5.3mm wide 74vhc373mtc mtc20 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide pin names description d 0 ? 7 data inputs le latch enable input oe output enable input o 0 ? 7 3-state outputs
74vhc373 octal d-type latch with 3-state outputs ?993 fairchild semiconductor corporation www.fairchildsemi.com 74vhc373 rev. 1.3 2 logic symbol ieee/iec truth table h = high voltage level l = low voltage level z = high impedance x = immaterial o 0 = previous o 0 before high-to-low transition of latch enable functional description the vhc373 contains eight d-type latches with 3-state standard outputs. when the latch enable (le) input is high, data on the d n inputs enters the latches. in this condition the latches are transparent, i.e., a latch output will change state each time its d input changes. when le is low, the latches store the information that was present on the d inputs a setup time preceding the high-to-low transition of le. the 3-state standard outputs are controlled by the output enable (oe ) input. when oe is low, the standard outputs are in the 2-state mode. when oe is high, the standard outputs are in the high impedance mode but this does not inter- fere with entering new data into the latches. logic diagram please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. figure 1. inputs outputs le oe d n o n xhx z hll l hlh h llx o 0
74vhc373 octal d-type latch with 3-state outputs ?993 fairchild semiconductor corporation www.fairchildsemi.com 74vhc373 rev. 1.3 3 absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. recommended operating conditions (1) the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. note: 1. unused inputs must be held high or low. they may not float. symbol parameter rating v cc supply voltage ?.5v to +7.0v v in dc input voltage ?.5v to +7.0v v out dc output voltage ?.5v to v cc + 0.5v i ik input diode current ?0ma i ok output diode current ?0ma i out dc output current ?5ma i cc dc v cc /gnd current ?5ma t stg storage temperature ?5? to +150? t l lead temperature (soldering, 10 seconds) 260? symbol parameter rating v cc supply voltage 2.0v to +5.5v v in input voltage 0v to +5.5v v out output voltage 0v to v cc t opr operating temperature ?0? to +85? t r , t f input rise and fall time, v cc = 3.3v ?0.3v v cc = 5.0v ?0.5v 0ns/v 100ns/v 0ns/v 20ns/v
74vhc373 octal d-type latch with 3-state outputs ?993 fairchild semiconductor corporation www.fairchildsemi.com 74vhc373 rev. 1.3 4 dc electrical characteristics noise characteristics note: 2. parameter guaranteed by design. symbol parameter v cc (v) conditions t a = units 25? ?0? to +85? min. typ. max. min. max. v ih high level input voltage 2.0 1.50 1.50 v 3.0?.5 0.7 x v cc 0.7 x v cc v il low level input v oltage 2.0 0.50 0.50 v 3.0?.5 0.3 x v cc 0.3 x v cc v oh high level output v oltage 2.0 v in = v ih or v il i oh = ?0? 1.9 2.0 1.9 v 3.0 2.9 3.0 2.9 4.5 4.4 4.5 4.4 3.0 i oh = ?ma 2.58 2.48 4.5 i oh = ?ma 3.94 3.80 v ol low level output voltage 2.0 v in = v ih or v il i ol = 50? 0.0 0.1 0.1 v 3.0 0.0 0.1 0.1 4.5 0.0 0.1 0.1 3.0 i ol = 4ma 0.36 0.44 4.5 i ol = 8ma 0.36 0.44 i oz 3-state output off-state current 5.5 v in = v ih or v il ; v out = v cc or gnd ?.25 ?.5 ? i in input leakage current 0?.5 v in = 5.5v or gnd ?.1 ?.0 ? i cc quiescent supply current 5.5 v in = v cc or gnd 4.0 40.0 ? symbol parameter v cc (v) conditions t a = 25? units t yp. limits v olp (2) quiet output maximum dynamic v ol 5.0 c l = 50pf 0.6 0.9 v v olv (2) quiet output minimum dynamic v ol 5.0 c l = 50pf ?.6 ?.9 v v ihd (2) minimum high level dynamic input voltage 5.0 c l = 50pf 3.5 v v ild (2) maximum low level dynamic input voltage 5.0 c l = 50pf 1.5 v
74vhc373 octal d-type latch with 3-state outputs ?993 fairchild semiconductor corporation www.fairchildsemi.com 74vhc373 rev. 1.3 5 ac electrical characteristics notes: 3. parameter guaranteed by design. t oslh = |t plh max ?t plh min |; t oshl = |t phl max ?t phl min| 4. c pd is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. average operating current can be obtained by the equation: i cc (opr.) = c pd ?v cc ?f in + i cc /8 (per latch). the total c pd when n pcs. of the latch operates can be calculated by the equation: c pd (total) = 14 + 13n. ac operating requirements symbol parameter v cc (v) conditions t a = +25? t a = ?0? to +85? units min. typ. max. min. max. t plh , t phl propagation delay time (le to o n ) 3.3 ?0.3 c l = 15pf 7.0 11.0 1.0 13.0 ns c l = 50pf 9.5 14.5 1.0 16.5 5.0 ?0.5 c l = 15pf 4.9 7.2 1.0 8.5 ns c l = 50pf 6.4 9.2 1.0 10.5 t plh , t phl propagation delay time (d to o n ) 3.3 ?0.3 c l = 15pf 7.3 11.4 1.0 13.5 ns c l = 50pf 9.8 14.9 1.0 17.0 5.0 ?0.5 c l = 15pf 5.0 7.2 1.0 8.5 c l = 50pf 6.5 9.2 1.0 10.5 t pzl , t pzh 3-state output enable time 3.3 ?0.3 r l = 1k ? c l = 15pf 7.3 11.4 1.0 13.5 ns c l = 50pf 9.8 14.9 1.0 17.0 5.0 ?0.5 c l = 15pf 5.5 8.1 1.0 9.5 ns c l = 50pf 7.0 10.1 1.0 11.5 t plz , t phz 3-state output disable time 3.3 ?0.3 r l = 1k ? c l = 50pf 9.5 13.2 1.0 15.0 ns 5.0 ?0.5 c l = 50pf 6.5 9.2 1.0 10.5 t oslh , t oshl output to output skew 3.3 ?0.3 (3) c l = 50pf 1.5 1.5 ns 5.0 ?0.5 c l = 50pf 1.0 1.0 c in input capacitance v cc = open 4 10 10 pf c out output capacitance v cc = 5.0v 6 pf c pd po w er dissipation capacitance (4) 27 pf symbol parameter v cc (v) t a = +25? t a = ?0? to +85? units min. typ. max. min. max. t w (h) minimum pulse width (le) 3.3 ?0.3 5.0 5.0 ns 5.0 ?0.5 5.0 5.0 t s minimum set-up time 3.3 ?0.3 4.0 4.0 ns 5.0 ?0.5 4.0 4.0 t h minimum hold time 3.3 ?0.3 1.0 1.0 ns 5.0 ?0.5 1.0 1.0
74vhc373 octal d-type latch with 3-state outputs ?993 fairchild semiconductor corporation www.fairchildsemi.com 74vhc373 rev. 1.3 6 physical dimensions dimensions are in inches (millimeters) unless otherwise noted. figure 2. 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide pa ck ag e number m20b
74vhc373 octal d-type latch with 3-state outputs ?993 fairchild semiconductor corporation www.fairchildsemi.com 74vhc373 rev. 1.3 7 physical dimensions (continued) dimensions are in millimeters unless otherwise noted. figure 3. 20-lead small outline package (sop), eiaj type ii, 5.3mm wide pa ck ag e number m20d
74vhc373 octal d-type latch with 3-state outputs ?993 fairchild semiconductor corporation www.fairchildsemi.com 74vhc373 rev. 1.3 8 physical dimensions (continued) dimensions are in millimeters unless otherwise noted. figure 4. 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide pa ck ag e number mtc20
74vhc373 octal d-type latch with 3-state outputs ?993 fairchild semiconductor corporation www.fairchildsemi.com 74vhc373 rev. 1.3 9 tradem a rks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intend ed to be an exhaustive list of all such trademarks. acex across the board. around the world. activearray bottomless build it now coolfet crossvolt ctl current transfer logic dome e 2 cmos ecospark ensigna fact quiet series fact fast fastr fps frfet globaloptoisolator gto hisec i-lo implieddisconnect intellimax isoplanar microcoupler micropak microwire msx msxpro ocx ocxpro optologic optoplanar pacman pop power220 power247 poweredge powersaver powertrench programmable active droop qfet qs qt optoelectronics quiet series rapidconfigure rapidconnect scalarpump smart start spm stealth superfet supersot -3 supersot -6 supersot -8 syncfet tcm the power franchise tinyboost tinybuck tinylogic tinyopto tinypower tinywire trutranslation p serdes uhc unifet vcx wire disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. these specifications do not expand the terms of fairchild? worldwide terms and conditions, specifically the warranty therein, which covers these products. life support policy fairchild? products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems wh ich, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform w hen properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information formative or in design this datasheet contains the design specifications for product development. specifications may change in any manner without notice. preliminary first production this datasheet contains preliminary data; supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice to improve design. no identification needed full production this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice to improve design. obsolete not in production this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. re v. i24
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